Fig. 3-7- Page 50

CHAPTER 3  THEORY OF OPERATION

3-8

A Fujitsu 32bit RISC CPU, MB86832 (SPARC lite) is built in the ASIC.  While the CPU is driven
with a clock frequency of 33 MHz in the user logic block, it itself runs at 66 MHz, which is
generated by multiplying the source clock by two.

The functions of the interface block communication with external devices are described below;

(1) IEEE1284

Stores the data received from the PC into DRAM as controlled by the DMA controller.  It is
applicable to both normal receiving and bi-directional communication (nibble mode, byte
mode, ECP mode).

(2) USB interface

Stores the data received from the PC into DRAM as controlled by the DMA controller.  The
transmission speed is 12Mbps.

(3) Engine GA transfer circuit

Communicates with the engine GA by a full-duplex synchronous serial method.  The
communication speed is 2Mbps.

(4) PCI interface (for HL1270N only)

Sends and receives the data to and from the Ethernet controller ‘AM79C973AKC’.  It is PCI
specification revision 2.2 compliant.

HL-1250/1270N