Fig. 3-16; Fig. 3-17; Optional serial I/O- Page 57

CHAPTER 3  THEORY OF OPERATION

3-15

  1.3.6

Optional serial I/O

The interrupt of the serial I/O is input to the EXINT terminal of the ASIC, and is recognized by
the CPU.  A 32-byte register is provided for this I/O, which is read from and written to by the
CPU.

Fig. 3-16

  1.3.7

PCI bus

The interface of the PCI bus is PCI specification revision 2.2 compliant.

Fig. 3-17

HL-1250

HL-1270N