Fig. 3-22; Fig. 3-23; Fig. 3-24- Page 59

CHAPTER 3  THEORY OF OPERATION

3-17

The reset IC is a RN5VD42A.  The reset voltage is 4.2V (typ.) and the LOW period of reset is
80ms (typ.)

Fig. 3-22

  1.3.10 Engine I/O

Fig. 3-22 shows the engine interface circuit.  The interface with the engine PCB is by full-
duplex synchronous serial method.

Fig. 3-23

Fig. 3-23 shows the engine interface circuit.  The interface with the engine PCB is by full-
duplex synchronous serial method.

Fig. 3-24

HL-1250/1270N

HL-1250/1270N

HL-1030/1240